It is known, e.g. from that commonly owned prior patent or from U.S. Pat. No. 3,441,870, to adjust the output frequency f.sub.A of a slave oscillator with the aid of a phase-locking loop driven by a reference frequency f.sub.B, the magnitude f.sub.A = gf.sub.B of that output frequency being variable in digital increments by means of a settable frequency divider of integral step-down ratio g : 1 in the loop. The frequency increments available in such a system are equal to the reference frequency f.sub.B or multiples thereof.
For various reasons, such as greater susceptibility to noise interference and more sluggish response to adjusting operations, practical lower limits exist for the choice of the reference frequency f.sub.B ; thus, the output frequency f.sub.A can be varied only in relatively coarse steps. Fractional increments can be obtained, as described in U.S. Pat. No. 3,441,870, by varying the division factor g of the divider in different cycles of the reference frequency f.sub.B and averaging the resulting values of output frequency f.sub.A with the aid of a smoothing circuit designed to minimize distortions due to the periodic switchover. This smoothing circuit becomes more effective with an increase in its time constant which, however, again retards any adjustment of the system.